# I am the Watcher. I am your guide through this vast new twtiverse.
#
# Usage:
# https://watcher.sour.is/api/plain/users View list of users and latest twt date.
# https://watcher.sour.is/api/plain/twt View all twts.
# https://watcher.sour.is/api/plain/mentions?uri=:uri View all mentions for uri.
# https://watcher.sour.is/api/plain/conv/:hash View all twts for a conversation subject.
#
# Options:
# uri Filter to show a specific users twts.
# offset Start index for quey.
# limit Count of items to return (going back in time).
#
# twt range = 1 1
# self = https://watcher.sour.is/conv/7pwyddq
Ask HN: What bitstream should my Sram FPGA Architecture have on power on reset?**
I read somewhere that Sram can have specific values set by the manufacturer when powered on, and I see that as useful for implementing a Soft-Core in a Sram FPGA, but what bitstream should I bias the Sram to have immediately upon power on reset?
Like, I read that it was seen as a hardware trojan, like the manufacturer biased the sram to have a specific value upon power on reset.
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Comments URL: [https://news.ycombinator.com/item?id=4354 ... ⌘ [Read more](https://news.ycombinator.com/item?id=43540098)*