# I am the Watcher. I am your guide through this vast new twtiverse.
# 
# Usage:
#     https://watcher.sour.is/api/plain/users              View list of users and latest twt date.
#     https://watcher.sour.is/api/plain/twt                View all twts.
#     https://watcher.sour.is/api/plain/mentions?uri=:uri  View all mentions for uri.
#     https://watcher.sour.is/api/plain/conv/:hash         View all twts for a conversation subject.
# 
# Options:
#     uri     Filter to show a specific users twts.
#     offset  Start index for quey.
#     limit   Count of items to return (going back in time).
# 
# twt range = 1 1
# self = https://watcher.sour.is/conv/szjcrhq
linux_gizmos
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Renesas reveals its first 32-bit RISC-V CPU
Renesas Electronics recently announced the release of its first 32-bit CPU core based on the RISC-V open-standard instruction set architecture (ISA). This development represents Renesas’ entry into the RISC-V based market. The new CPU core will be compatible with Renesas’ e2 studio IDE, in addition to supporting third-party IDEs tailored for RISC-V based MCUs, facilitating […] ⌘ Read more